1. Field of the Invention
The present invention relates to a program and method for balancing the loads on channel paths in a digital computer. More particularly, the invention relates to a program and method for balancing the loads on channel paths in a digital computer during long running applications.
2. Discussion of the Related Art
Modern computers require a host processor including one or more central processing units and a memory facility. The processor manipulates data stored in the memory according to instructions provided to it. The memory must therefore be capable of storing data required by the processor and transferring that data to the processor at a rate capable of making the overall operation of the computer feasible. The cost and performance of computer memory is thus critical to the commercial success of a computer system.
Because today's computers require large quantities of data storage capacity, computer memory is available in many forms. A fast but expensive form of memory is main memory, typically comprised of microchips. Other available forms of memory are known as peripheral storage devices and include magnetic direct access storage devices (DASD), magnetic tape storage devices, optical recording devices, and magnetic or optical mass storage libraries. Each of these other types of memory has a greater storage density and thus lower cost than main memory. However, these other memory devices do not provide the performance provided by main memory. For example, the time required to properly position the tape or disk beneath the read/write mechanism of the drive cannot compare with the rapid, purely electronic data transfer rate of main memory. It is inefficient to store all of the data in a computer system on but a single type of memory device. Storing all of the data in main memory is too costly and storing all of the data on one of the peripheral storage devices reduces performance.
A typical computer system includes both main memory and one or more types of peripheral storage devices arranged in a data storage hierarchy. The data storage hierarchy arrangement is tailored to the performance and cost requirements of the user. In such a hierarchy, main memory is often referred to as primary data storage, the next level of the hierarchy is often to referred to as secondary data storage, and so on. Generally, the highest level of the hierarchy has the lowest storage density capability, highest performance and highest cost. As one proceeds down through the hierarchy, storage density generally increases, performance generally decreases, and cost generally decreases. By transferring data between different levels of the hierarchy as required, the cost of memory is minimized and performance is maximized. Data is thus stored in main memory only so long as it is expected to be required by the processor. The hierarchy may take many forms, include any number of data storage or memory levels, and may be able to transfer data directly between any two distinct memory levels. The transfer of data may employ I/O channels, controllers, or cache memories as is well known in the art.
In a typical computer using main memory as primary data storage and peripheral storage devices as secondary data storage, the processor can only access data for executing instructions if the data is stored in main memory. If work to be done by the processor requires data not then stored in main memory, the processor will recall or promote data from the peripheral storage device to main memory. A processor may recall data simply to access or change that data, or for other reasons, such as data storage management. Examples of data storage management include the migration of data to a lower level of the data storage hierarchy and the copying of a data set to create a "backup" copy of that data set. Access to the data occurs using one or more channel paths connected between the processor and the peripheral storage device.
Generally, it is desirable to distribute the load of data transfers across the channel paths (such distribution is hereinafter known as "balancing") to promote efficient operations. For example, it would not be efficient to perform the aforementioned data transfers using but one of a plurality of available channel paths. The one, utilized channel path would be unduly loaded while the remaining available channel paths would be wasted. In addition, a malfunction of the utilized channel path could result in a significant delay in processing. By dividing the load across the channel paths processing is accomplished with less load per channel path and the significance of any single channel path malfunction is reduced.
Several techniques are known for balancing the use of resources in a data processing system. Such balancing among resources is usually achieved at task assignment time. That is, before any processing ensues a control mechanism determines which resource should handle the task. Examples of such task assignment balancing are found in the IBM Technical Disclosure Bulletin, Vol. 20, No. 3, August, 1977, pp 937-38, the IBM Technical Disclosure Bulletin, Vol. 14, No. 11, April, 1972, pp. 3458-3459, U.S. Pat. No. 3,648,253 and U.S. Pat. No. 4,032,899.
Load balancing may be enhanced by monitoring the activity of system resources. The monitoring of resources permits the system to subsequently re-allocate the use of such resources. Typically, resource activity is monitored for a period of time to determine which resources are overutilized and which resources are underutilized. Load balancing is then achieved during the subsequent assignment of tasks. An example of such monitoring is found in IBM Technical Disclosure Bulletin, Vol. 24, No. 1B, June, 1981, pp. 707-09 and U.S. Pat. No. 3,588,837.
Not all load balancing is achieved at task assignment time. By monitoring resources after task assignment, as previously described, dynamic load balancing is achieved. Tasks causing the overutilization of a particular resource are discontinued or re-assigned to other resources. An example of such load balancing is found in IBM Technical Disclosure Bulletin, Vol. 24, No. 3, August, 1981, page 1411. U.S. Pat. No. 4,633,387 discloses a system in which resources monitor themselves. A least busy resource requests work from a busier resource when its work falls below a threshold level. The busier resource then supplies work to the requesting unit to balance the respective loads.
The aforementioned methods of load balancing do not achieve such over a prolonged duration. This is the result of a failure to account for the duration of a load associated with the assignment of a task or a failure to anticipate load duration during the monitoring of resources. There is little advantage to assigning a task to a resource having low activity if the task is of short duration. During processing of such a task, other tasks of longer duration may be assigned to otherwise (not including the assigned task of short duration) more active resources, thereby resulting in short term load balancing and long term load unbalancing. Similarly, the expected duration of different resource activities should be monitored, not just their peak or average load.
The aforementioned methods also fail to account for certain situations actually requiring some degree of load unbalancing. Resources connected to devices having affinity to a certain host for processing should be selected for processing on that host before resources which can be processed by any host. Also, if the availability of resources to some extent depends on their lack of use, it may be desirable to allocate such resources so as to maintain that lack of use. Finally, load balancing should account for system connections to maintain maximum availability of resources connected to the most system devices.